In accordance with the prior art, multi-layer active matrix displays are well known. Conventional thin film transistors (TFT) are typically fabricated with inorganic silicon, such as amorphous silicon or polycrystalline silicon. Silicon based processes require a combination of vacuum deposition and subtractive photolithographic patterning steps leading to high capital equipment, materials and manufacturing costs. The most common active matrix display technology is the thin film transistor liquid crystal display (LCD), where applications range from PDA and notebook devices to flat screen televisions. Active matrix displays are also used in combination with emerging display effects such as organic light emitting diodes (OLED) and electronic paper. In many conventional pixel configurations the presence of the pixel capacitor reduces the aperture ratio.
Active matrix displays, where the pixel voltage or current is controlled by one or more transistors, dominate flat panel display design. One of the key elements of an active matrix display pixel is the pixel capacitor, formed between each of the pixel electrodes and an interconnect line at a fixed potential. The interconnect line can be a separate metallic line held at a fixed potential (usually ground potential) during the addressing of the active matrix, or it can be the (N−1)th or (N+1)th neighbouring TFT gate addressing line, that is kept at a fixed potential while the Nth gate addressing line is being addressed. This configuration is most common because it does not require a third additional set of interconnect lines running across the display, as would be the case where there is a separate bus line.
The manufacture of active matrix displays by solution based print processes offers many potential advantages over conventional manufacturing methods. In principle, solution based print processes are environmentally friendly, low temperature, compatible with flexible substrates, cost effective and advantageous for short run length and large display sizes. However, fabrication of high-resolution displays by printing processes is challenging. When using printing processes such as additive inkjet printing, screen printing and offset printing or subtractive direct-write patterning processes laser ablation it is difficult to fabricate metallic interconnect lines with a width of less than 50-100 μm because of the difficulties associated with delivering small volumes of liquid. Furthermore, many printable conductors such as conducting polymers or colloidal metals have conductivities significantly lower than bulk copper or silver, therefore requiring thick and wide interconnect lines to achieve adequate conductance across a large active matrix. Therefore, by using conventional display architectures, printed components can tend to be large and result in active matrix displays with low aperture ratios. FIG. 2 shows a known multi-layer structure with a continuous top pixel electrode deposited over the gate electrode.
One problem that is shared between conventional TFT technology and semiconducting polymer-based printed TFTs alike is the limited display area, in which the thin film transistor, the gate line, the pixel capacitor and the pixel itself compete with each other for space. This can lead to a reduction in the aperture ratio and therefore the quality of the display. The aperture ratio of the display is defined by the area of the pixel electrode divided by the area of the pixel footprint. Since the pixel electrode is competing for space in the pixel footprint, it is preferable to use a multi-level structure where the pixel electrode is defined on a different layer from the interconnect and data lines. When fabricating such an electrode it is advantageous to use an organic conductor because it can be processed from solution, which facilitates the process of via-hole filling and allows for low cost deposition techniques. A schematic of a prior art architecture is shown in FIGS. 1 to 3.
In our patent application PCT/GB2006/050078 a four or five layer architecture structure is disclosed where the pixel capacitor can be formed with one of the two electrodes of a pixel capacitor being quasi-continuous. In such a case, the pixel capacitance becomes largely insensitive to the detailed position of the other of the electrode. This can be achieved, for example, by running a straight common electrode (COM) line with a given line width smaller than the pixel pitch behind the pixel electrode. The correct pixel capacitance can be tuned by the capacitance (thickness and dielectric constant of the pixel capacitor dielectric 8). Even for a wide linewidth a small pixel capacitance can be achieved if needed by choosing a relatively thick pixel dielectric. In this structure the value of the pixel capacitance is independent of the exact location of the COM line behind the pixel electrode, as long as the COM line is fully running below the pixel electrode, and does not begin to overlap with the neighbouring pixel electrode. By choosing an appropriately thick dielectric between the COM line and the TFT layers, any contribution to the pixel capacitance from overlap of the COM line with the drain electrode of the TFT in the first layer is negligible. This leads to a highly uniform value of the pixel capacitance across the pixel array, which is an important requirement for grey scale displays.
The object of the present invention relates to an electronic device incorporating an off-set pixel electrode achieving increased storage capacitance.